1. Field of the Invention
The present invention relates to the fabrication of semiconductor components, and more particularly to the fabrication of so-called "Smart Power" components that include power elements, usually vertical MOS transistors, and a control logic portion on the same silicon chip.
2. Discussion Of the Related Art
To produce such components, both power and logic circuit technologies must be used together. This involves in particular major differences in the size of connections, formed as metallizations. In fact, the density of the metallizations in the logic portion of the component must be very high, which requires, for technical reasons, that the metallizations be substantially thin. A rule commonly followed is that the thickness of the metallization must be smaller than one half of its width. This is not a major impairment for metallizations of logic circuits that conduct low currents corresponding to logic signals. In contrast, high currents flow through the metallizations in the power portion of the component which, accordingly, must be wider and thicker than the metallization in the logic portion.
In the prior art, various techniques have been proposed to form "thin" and "thick" metallizations using as few steps as possible. It should be noted that even though reference is made to "thick" metallizations, the invention relates to thin layer technology, that is, these "thick" metallizations have thicknesses ranging from 1 to 4 .mu.m and more frequently from 2 to 3 .mu.m, whereas the so-called "thin" metallizations have thicknesses smaller than 1 .mu.m.
FIGS. 1A-1D illustrate successive steps of a method to form metallizations according to the prior art. These figures are schematic cross-sectional views.
FIG. 1A represents a substrate 1, usually a silicon substrate, in which desired diffused structures have been formed and that may be locally coated with insulation layers, gate regions, etc. A first layer 2 made from a conductive metallic material is deposited on the substrate. The thickness of the first metal layer 2 is designed to form conductive connections for the logic portion of the component. A layer 3, made from a photosensitive material used for photolithography, and hereinafter referred to as a resist layer, is deposited on the first metal layer 2. The first resist layer 3 is formed with regions that substantially correspond to the desired thin and thick connections to be subsequently formed.
As illustrated in FIG. 1B, a photoetching step forms first metal regions M1-1 and M1-2 that correspond to the connections of the logic portion of the component, and a second metal region M1-10 that corresponds to a power portion connection. Thereafter, the first metal regions M1-1 and M1-2 are coated with a protection layer 5; the protection layer 5 having an aperture 6 corresponding to the second metal region M1-10. The formation of the aperture 6 in layer 5 is formed by a resist deposition and photoetching step.
In the step illustrated in FIG. 1C, a second metal layer 7 and a second resist layer 8 are deposited on the substrate 1. The second resist layer 8 is formed to substantially correspond to the second metal region M1-10.
FIG. 1D represents the state of the structure after etching of the second metal layer 7. As shown, portions of the second metal layer M2-10 remain over some corresponding regions M1-10 of the first metal layer.
Thus, this method involves three photoetching steps: a first step for the first metal layer 2, a second step for the protection layer 5, and a third step for the second metal layer 7. As known, an etching operation is relatively difficult to perform and is time consuming. Another drawback of the structure of FIG. 1D is that the material of the protection layer 5 must be selected from among a relatively limited number of materials, if it is desired to maintain the material of the protection layer in place at the final step, because the material then must necessarily be an insulating material. A further drawback of the illustrated method is that the second metallization does not fully cover the first metallization to account for possible misalignment of the masks. As shown in FIG. 1D, the protection layer 5 mush slightly cover the periphery of the first metallization near the second region M1-10. Additional problems are raised if it is desired to eliminate the protection layer 5 because a lateral sub-etching will then occur at the periphery of the metal regions M1-10 and M2-10.
To reduce the number of photoetching operations, it has been proposed in the prior art to remove layers by etching and lifting-off underlying layers, but these steps are difficult to industrially control and cause pollution.